41st Conference on Design of Circuits and Integrated Systems
DCIS 2026

Bram Nauta, University of Twente

Talk title and abstract to be announced

Francesc Moll, UPC/BSC

Beyond the Logic Core: RISC-V, Mixed-Signal Bottlenecks, and the Path to Sovereign European HPC

High-Performance Computing (HPC) sits at the epicenter of technological sovereignty, driving everything from exascale AI and climate modeling to national security. While initiatives like the European Processor Initiative (EPI), EUPilot, DARE, and the Barcelona Zettascale Lab have successfully demonstrated that open-standard RISC-V logic (CPUs, VPUs, and AI accelerators) can power future supercomputers, a critical reality remains: compute silicon does not exist in a vacuum.

A sovereign CPU or vector unit is only as capable as the system supporting it. This keynote explores the architectural anatomy of sovereign HPC compute engines and confronts the “missing pieces” in the European design ecosystem. We examine why the key bottlenecks to true hardware independence are shifting from digital logic to advanced analog/mixed-signal IP (PHYs for HBM3/4, LPDDRx, PCIe, and UCIe die-to-die chiplet interfaces), open EDA scaling, and 2.5D/3D packaging realities. Finally, we highlight the central role of Academia and Research Technology Organizations (RTOs) in training the next generation of microelectronic engineers, bridging the lab-to-fab gap through pilot lines, and using open-source IP to transform theoretical research into physical, production-ready silicon.